Configurable CIC Filter by Christopher L. Felton

Has anyone successfully created a Verilog or vhdl of the above project?

I have been trying to reproduce the Configurable CIC Filter that is presented here. I downloaded the latest release (cic-0.3.tar.gz). I run the following python code to create a Verilog output and get the subsequent error if Type is set to other than None.:

from cic_hdl import *
M = 3
D = 2
R = 8
Q = 24
Type = ‘Dec’

Parameters / Globals

MaxGain = DM# Max gain of the CIC
L = 2
(Q)# Max value for input
maxV = L * 2*MaxGain# Max Value for output
minV = -maxV# Min Value for output


clk = Signal(False)
rst = Signal(False)
x = Signal(intbv(0, min=-L, max=L))
y = Signal(intbv(0, min=minV, max=maxV))
dvi = Signal(True)
dvo = Signal(False)

toVerilog(cic_filter, clk, rst, x, dvi, y, dvo, M, D, R, Q, Type)

Python 2.7.12 (v2.7.12:d33e0cf91556, Jun 27 2016, 15:24:40) [MSC v.1500 64 bit (AMD64)] on win32
Type “copyright”, “credits” or “license()” for more information.

RESTART: D:\Electronics\Digital Filter\MyHdl CIC\releases\cic-0.3\hdl\
decimate Qc 3 R 8

Traceback (most recent call last):
File “D:\Electronics\Digital Filter\MyHdl CIC\releases\cic-0.3\hdl\”, line 27, in
toVerilog(cic_filter, clk, rst, x, dvi, y, dvo, M, D, R, Q, Type)
File “C:\Python27\lib\site-packages\myhdl\”, line 152, in call
siglist, memlist = _analyzeSigs(h.hierarchy)
File “C:\Python27\lib\site-packages\myhdl\”, line 107, in _analyzeSigs
raise ConversionError(_error.UndefinedBitWidth, s._name)
ConversionError: Signal has undefined bit width: Dec_cnt

1 Like

@KingJL yes I have converted this to Verilog and VHDL, this version is quite old though. My local version has evolved over the years. I will see can post an updated version somewhere.

Thank you for the reply… truly! I kind of figured that you had! I am very new to MyHhdl and trying to wrap my old brain (old dog (73)… new tricks) around it. I have done some FPGA programming in VHDL for a Spartan 6 and used Python matplotlib during testing to display the results. I would like to get away from the Xilinx proprietary cores for my filters that I have been using and get to Verilog and VHDL IP’s. I thought I may as well give MyHdl a try at the same time. I am thinking of moving to a Arty (Artix 7) development board. One of the first filters I need to implement is a CIC… next in line is a FIR compensation filter for the CIC.

I had come to the conclusion that the version of your "Configurable CIC ", that I was using, was probably dated. But searches for a more recent version and some documentation of the implementation were fruitless. Access to an updated version of the Configurable CIC would help me in my both my quests… to a non proprietary (open) IP core and learn MyHdl! Thanks again for the reply.


sounds like you would to achieve similar things like me! I’m working on the python based tool pyFDA for filter design and analysis ( and I’m still planning to export VHDL / Verilog Code for FIR and IIR filters in the hopefully not too far future. I’m also working with Xilinx Series 7 FPGAs.

I played around a little with myHDL but got tangled in other stuff. A CIC filter would be a nice start for an HDL export (and for me, to learn myHDL as well). Do you plan to run simulations with myHDL as well? If you are interested, we could try to integrate the myHDL CIC module in pyFDA for simulation (ideal, this is implemented already), synthesis / fixpoint simulation with myHDL.
@cfelton: Christopher, I would be interested in an updated version of your CIC module as well :slight_smile: that can be converted with the current version of myHDL!

1 Like

@chipmuenk, we have a gsoc student that will be working on the fixbv compiler (fixed-point compilation). That should be interesting and applicable work for your project.

I have a couple outstanding configurable filter blocks that could be used in pyfda, some are changes in made in the pyfda space but haven’t pushed. I will create a small package for these filters (cic, basic fir, and basic iir). Then we can decide if it should be part of pyfda or separate.


@cfelton, sounds terrific! I guess it would be better for maintainability to keep your filter package separate from pyfda and invest some time in defining the interface (coefficients, topology, wordlengths, simulation / plot data …). But perhaps it is a bit early for a discussion without having seen the code :wink:



@chipmuenk, I have been following the pyFDA project and found it extremely interesting… can’t wait to try the VHDL/Verilog export when it is available.

I think the error is in the interp and decim methods, the local variable cnt is declared as intbv without a min. I added min=0 to this intbv and it added the interpolation/decimation to the output verilog and stopped returning that error.

change cnt = Signal(intbv(0, max=2**Qc))


change cnt = Signal(intbv(0, min=0, max=2**Qc))

in both and


One additional question I have about this implementation is that the upsample seems to be added before the combs, whereas in a typical CIC interpolation filter the resample comes between the combs and integrator, allowing the comb to be run at a slower clock rate. In fact this implementation seems to run combs and integrators at the same rate, negating the need for interpolation…just curious.

Nice implementation and I have learned a lot about implementing filters in myhdl from this!


@Jeffrey_Walling, Thank you! Now I can play!!!

Thanks! I’m looking forward to doing more “fun stuff” again - in the last months I’ve worked more on infrastructure and UI stuff.