VHDL constant value overflow

[mhavu]

@DrPi

We already spoke about this before in other threads. I think we need constants in MyHDL.
I already started to code such a functionality but only for VHDL, not for verilog.

Do you mean this one? What do you guys think about adding generics support in the constant type? In my opinion, the constructor for the constant type could have a named parameter with default value parameter=False. If parameter were set to True, a generic would be generated instead of a constant.