REG intialization without 'always_seq' (solved)


#1

http://fpga-designs-with-myhdl.readthedocs.io/en/latest/myhdl/fsm.html#square-wave-ex-py

  • In the above link, the signal ‘t’ (at Line 20) is initialized using ‘always_seq’ decorator; which uses the ‘reset’ signal to set the initial value.

  • Is is possible to generate the Verilog/VHDL code as "reg [3:0] t = 0 ", instead of using reset signal to set the initial value.


#2

Initial value is always supported in simulation.
It is also supported in conversion when using the last version on github.


#3

It is not working.
I installed MyHDL using conda and pip. Did I do something wrong with installation.
Python Version : 3.6.2, MyHDL 0.9.0.

I tried with MyHDL 1.0 as well, but after conversion, the reg is defined as “reg [3:0] t” (not as reg [3:0] t = 0).


#4

Have you used set initial_values parameter to True when converting ?
Something like :
dut_inst.convert(hdl=‘VHDL’, name=“RandomGenerator”, path="./vhdl", initial_values=True)


#5

Thank you.

It worked with MyHDL 1.0.
Previously, I was using .covert function with MyHDL 0.9.0, that is why I was getting error.