How do MyHDL people usually work around the VHDL size limit for integer literals? Consider the following MyHDL code:
Y_LEN = 71
Y_MIN, Y_MAX = (-2**(Y_LEN - 1), 2**(Y_LEN - 1))
y = Signal(intbv(0, Y_MIN, Y_MAX))
# An attempt to implement saturation somewhere in the code
if result < 0:
accumulator.next = Y_MIN
else:
accumulator.next = Y_MAX - 1
This converts to VHDL as follows:
if (result < 0) then
accumulator <= signed'("11111111111111111111111111111111111100000000000000000000000000000000000");
else
accumulator <= to_signed(34359738368 - 1, 71);
end if;
The first case translates to a bit string literal, which is fine (although hexadecimal would be much easier to read than binary at these lengths). The second case with the arithmetic operation translates to an integer literal that is too large – at least as far as the compiler is concerned. Tweaking the constants would take care of this, but all the added plus ones and minus ones are not exactly good for reducing off-by-one errors. Are there any other options?