I have a tinyfpga board with e external FAULT signal which is active low and should in practice always stay high or otherwise the ‘machine’ is stopped until reset again.
My problem is: The machine is always stopped - ENABLE is low.
I initialize FAULT, ENABLE to be 1.
ie. in the pin config as follows:
set_io -pullup yes FAULT D9 #pin 15
and in the testbench:
FAULT = Signal(intbv(1)[1:])|
ENABLE= Signal(intbv(1)[1:])
Experiments with the following program show that at some time the FAULT must be read zero and the ‘machine’ gets halted - ENABLE is 0.
If i set FAULT to (fix) 1 in my program this will not happen and ENABLE is 1.
The FAULT input is treated ‘as usual’ with a synchronization flip flop or two for input.
I wrote some comments on my experiments in def negedge_detect() in the program.
Somebody sees what’s wrong here?
# unit_standalone tests only a interrupt with help of a led
# convert with run_standalone.py and upload to tinyfpga
from myhdl import *
@block
def unit_standalone(CLK,LED,USBPU,RESET,ENABLE,FAULT,CLK4M,CLK8K,MISO,MOSI,SCLK,RXRDY,TXRDY,SS_N,S1,S2,S3,S4,S5,S6,S7,RELAY,n,nspi):
maxd=2
clk4M = Signal(bool(0))
clk2M = Signal(bool(0))
pwmcounter = Signal(modbv(0, min=0,max=2**11)) #this counter is fix 11 bits for 16MHz CLK and 8kHz loop
slowcounter= Signal(modbv(0, min=0,max=2**14)) #this counter is uses to produce RELAY_trig 2s after start
#helpers:
Fault_d = Signal(bool(1))
Fault_dd= Signal(bool(1))
Fault_ddd= Signal(bool(1))
flag = Signal(bool(0))
latch = Signal(bool(0))
@always_seq(CLK.posedge, reset=RESET) #CLK is 16MHz
def clocks():
pwmcounter.next=pwmcounter+1
CLK4M.next = pwmcounter[1] #8MHz for edge delay is output
clk2M.next = pwmcounter[2] #2MHz for edge delay
CLK8K.next = pwmcounter[10] #8kHz control loop clock is output
@always_seq(flag.posedge, reset=RESET)
def haltpwm():
ENABLE.next=0
@always_seq(CLK8K.negedge, reset=RESET)
def probes():
if ENABLE:
LEDLat.next=not LEDLat
LED.next=LEDLat #debug: indicate with toggling led
else:
LED.next= 0
@always_seq(CLK.posedge,reset=RESET)
def negedge_detect():
Fault_d.next=FAULT # 1 asynchronous FAULT is simulated to be always 1
Fault_dd.next=Fault_d #therefore this is 1 too
flag.next= Fault_dd & ~Fault_d #as both are 1, flag is always 0 and ENABLE is always on as initialized so
#As soon as FAULT is used instead of a 1 the machine will not start, i.e. the led will not show.
return instances()
Therefore i assume that FAULT must have been 0 at some point in time since reset. How comes? Its an open pin and it is init to be 1. How to avoid this situation? (I tried a delay but no success).
The ‘testbench’ for conversion and interfacing is as follows:
import os
from myhdl import *
from unit_standalone import unit_standalone
from math import pi
print('run_standalone:')
print('defining bit width, defining external signals')
print('converting unit_standalone')
n=10 #bitwidth of internal signals limited by pwm counter to 11
nspi=16 #spi register width
def run_hw_bench(hdl):
CLK=Signal(bool(0))
LED=Signal(bool(0))
USBPU=Signal(bool(0))
RESET = ResetSignal(1,active = 0, isasync=True)
CLK8K = Signal(bool(0)) #-> use to sync dsp
MISO = Signal(bool(0))
MOSI = Signal(bool(0))
SCLK = Signal(bool(0))
SS_N = Signal(bool(0))
RXRDY = Signal(bool(0)) #rising edge: do now read rxdata
TXRDY = Signal(bool(0)) #rising edge: do now prepare txdata
CLK4M = Signal(bool(0)) #4MHz clock output to DSP
S1 = Signal(intbv(0)[1:]) #inverted output
S2 = Signal(intbv(0)[1:])
S3 = Signal(intbv(0)[1:])
S4 = Signal(intbv(0)[1:])
S5 = Signal(intbv(0)[1:])
S6 = Signal(intbv(0)[1:])
S7 = Signal(intbv(0)[1:])
RELAY = Signal(intbv(0)[1:])
FAULT = Signal(intbv(1)[1:])
ENABLE= Signal(intbv(1)[1:]) # enable pwm unit
dut = unit_standalone(CLK,LED,USBPU,RESET,ENABLE,FAULT,CLK4M,CLK8K,MISO,MOSI,SCLK,RXRDY,TXRDY,SS_N,S1,S2,S3,S4,S5,S6,S7,RELAY,n,nspi)
dut.convert(hdl=hdl)
run_hw_bench(hdl='Verilog')