I’m writing a unit test for some simple MyHDL and I’d like to know if it’s valid to call yield delay(0)
at the start of a test generator in order to make a combinatorial @always_comb
evaluate its outputs? If I don’t do this, then I find I need to delay for some arbitrary time until I can test the combinatorial output. Normally I could delay 1ns but then when I have a clock I’ll need a corresponding delay(N-1) to get back in sync with the clock.
An easy way to sync with a clock in a testbench is yield clock.posedge
1 Like
Thanks, that makes sense when waiting for the next clock. How about in a purely combinatorial design where there is no clock? What’s the best way to get the simulator to actually run a step and generate the driven outputs? yield delay(0)
does seem to work and propagate the assignments. I’m just not sure if it has some side-effects I’m not aware of yet.
yield delay(0)
will work fine, without side effects. You can see it as a delay with an infinitesimal small time …
The simulator will append a scheduled event with the same time.