MyHDL

Synthesizing RAM in Quartus Prime

According to the Quartus documentation on targetting embedded RAM, you must specify the directives in the Verilog code as comments. Is this the prescribed method when using this platform or is there another? Is there a way to propagate such a comment into the Verilog or must I edit the .v file after each compile?

Hi Kevin,

Unfortunately you will have to edit the .v file after every generation. To infer RAM storage we use the built-in type list which , even if we wanted to, can not not be augmented with attributes.

Regards,
Josy

Thank you, Josy. I opted for a work-around. It’s not perfect and it’s not parameterized, but it works.

    ...
    inst.convert(hdl=hdl)

if __name__ == '__main__':
    simulate(test_inst)
    convert()

    if not USE_QUARTUS:
        exit()

    import re

    # build the verilog filename just generated
    file = __file__.split('.')
    file[-1] = 'v'
    file = '.'.join(file)

    # update the file to patch the Quartus directive for using memory blocks    
    with open(file, 'r') as v:
        data = v.read()
    new_data = re.sub('(reg.*m9kb.*;)', r'(* ramstyle = "M9K" *) \1', data, flags=re.M)

    with open(file, 'w') as v:
        v.write(new_data)