At IMEC we use myhdl extensively for system exploration and design. Recently we migrated all our projects to the newest (github) version, and rewote the designs to use the block-decorator. Unfortunately this has a side effect in the vcd simulation results, for example
u_instA = some_moduleA(signal1…)
would end up as an entry ‘u_instA’ in the vcd file, but after migration the name was changed to use the module name + some number, like ‘some_moduleA_2’
This breaks our verification flow (where we use the vcd file to verify the output of the RTL simulation)
After a little digging we came up with a minor modification to mydhl_misc.instances() to restore the previous behaviour. Basically we extend the loop over all instances to copy the variable name to _Block instances, (overriding the name that was generated before). I am aware that this bypasses _uniqueify_name() in myhdl._block
Would that break something else in the flow?
I aim for inclusion in the mainline, so would an option be needed to make this behaviour switchable ?
kind regards, Paul