How to monitor enum signal

Support
1

Dear all,
I designed fsm with myhdl.enum type, but I cannot assign the enum type to other signals to monitor the state.
It reports expected int or intbv, got enum.

any suggest?

Thanks & regards
chriss

2

This is kind of a workaround, but it works:

a = Signal(int(0))
a.next = int(t_enumType.val1)
yield delay(2)

# To check state
assert a == int(t_enumType.val1)
3

Thanks, formulator, it works for simulation.

but, I want to wire the state to some register for monitor. Another workaround is to assign signals in each state case, but looks ugly.

4

Yes but, and correct me if I’m wrong, isn’t enum type is convertible to vhdl, and synthesizable?

5

definitely, it’s convertible. For FSM design, it’s useful.