How to pass part of the signal to module

I have module:

def addsub(clk, add, a, b, q):

def addsub_logic():
    if add == 1: = a + b
    else: = a - b
return addsub_logic

I want to create main module that will drive multiple instancies of addsub.
I need to slice d parameter and pass it to submodules. But how?
The example below doesn’t work.

def main(clk, d, q):
    res_l_0 = Signal(intbv(0, min=0, max=2**3))
    addsub_inst_0 = addsub(clk, intbv("1"), d[31:29], intbv("001"), res_l_0)

    res_l_1 = Signal(intbv(0, min=0, max=2**4))
    addsub_inst_1 = addsub(clk, res_l_0[2], d[29:27], concat("1", res_l_0[2], res_l_0[2], bool(0)), res_l_1)

I didn’t review your example in detail but this might help

An example of passing the part of ports is added at the below link,

In, following lines are used to pass the part of the signal to two different instances.

    # instantiation : 1-bit comparator
    eq0 = comparator_1_bit_proc(x=a(0), y=b(0), eq=s0)
    eq1 = comparator_1_bit_proc(x=a(1), y=b(1), eq=s1)