I’ve implemented inside _block.py a method for handling user code that allows more python-like naming of interface signals.
It’s currently a bit crude and currently only works for VHDL, but demonstrates the principle. Essentially, it allows signals to be included in VHDL_code like the following:
${interface_out.sig1} <= ${interface_in.sig1}
It neatly sidesteps the problem of potential name-space overlap - replacing at block creation time the interface string with the correct renamed string. It’s backwards compatible and safe insomuch as only the new style of names are changed (and only then in the case where it actually finds a suitable signal).
I was also wondering about LoS enhancement as well, but It’s not clear to me this is so simple (largely because I haven’t played with it to find out what they look like).
${signal_list_out[0]} <= ${signal_list_in[0]}