Programming Altera serial configuration device with Python

We’ve been programming a Cyclone 10 device using Quartus Prime and a USB blaster. Now, I would like to replace the USB blaster with an FTDI FT2232H device in MPSSE mode and bit bang the interface with a Python script that utilizes a programming file with an RBF extension. I’ve been searching for hours on this and can’t seem to find any solutions that are being used. Are there any recommendations on how to do this?

We used to bitbang Altera devices from the Cypress FX2 device.
I suggest you connect the FTDI device to the Cyclone in SPI -> Slave Serial Mode. Use a GPIO pin to control the Config_n input of the FPGA.
FTDI appnote:
If you take care you can later use the SPI interface to communicate with the downloaded logic - connect DCLK to another FPGA IO-pin.


Thank you for your reply. I can now easily see that I have made a error in the way I described my issue. I’m sorry for that.

We are actually not programming the Cyclone 10 device but rather the serial EEPROM that it is connected to using the ASMI interface. So, we program the EEPROM, cycle power, then the Cyclone 10 boots and loads from the EEPROM using its Active Serial mode.

I thought I remembered distinctly that there were tools (ap notes, implmentation examples, etc) on how to write code to load that EEPROM. I can’t find any so I thought I’d ask what the rest of the MyHDL community does in this use case.

Again, sorry for not being more precise.



But if you actually want to program that serial EEprom from the blank state via the FTDI, things get more complicated, and I am out my comfort zone then. We have never done that. Why not just keep on using the USB blaster?

Or if your application is USB-bound, load the FPGA from the PC as I suggested.

Or this: load a boot-logic into the FPGA using the SPI-mode I suggested. After that switch the SPI to control mode and write the serial EEprom. On the next power-on the FPGA can then boot from the serial EEprom. The remote update IP fromAltera/Intel may help:



I am developing an embedded system product and the device must be programmable from a blank state. No Quartus Prime and no USB Blaster will be available.

Also, the device has to power up ready to use. I will not have the luxery of starting the code and then loading the FPGA.

I will continue working this issue and get back with a solution if I find it.


@kc64 From what I understand, you have an embedded system with a µP and an FPGA. You want to be able to program the FPGA EEPROM from scratch with the µP.

Josy gave you one solution :

  • Design your system to enable the initialisation of the FPGA by the µP or the EEPROM (selected by software ?). I don’t use Intel FPGAs so I don’t know what is possible exactly.
  • Create one basic HDL design where the FPGA logic has access to the EEPROM.
  • When the EEPROM is blank (the FPGA is blank), load the basic HDL design in the FPGA.
  • Once the FPGA is initialised with the basic HDL design, program the EEPROM (through the FPGA)
  • Reboot the FPGA.

Another solution is to mux EEPROM pins between the FPGA and the µP. Then, you can initialise the EEPROM directly when it is blank.


@DrPi There is no µP in the design. An FTDI USB IC controls the FPGA. Other from that you spelled out my idea quite well.

There is an alternate solution to connect the FTDI device in SPI-mode parallel to the EPCS-FPGA connection. While keeping nConfig asserted (low) one can freely access the EPCS as an SPI slave.

You’re right. The fact that this is an embedded system made me think there is a µP.

@kc64 What is your problem exactly ? The schematics ? The way to control the FTDI chip from a Python application ?

@kc64 Besides programming the serial EEprom/Flash what other USB functionality do you want to use from the FTDI 2232H device?

Thank you all for your kind help and suggestions. My original intention was to try to find the resources I thought I had seen before (tech notes, code snippets) that direct how the EEPROM may be programmed using an RBF file from Quartus Prime.

The FT2232 has two mode that I will use. The primary one is Host Bus Emulation (HBE) where most of the FT2232 pins mimic an 8051 system interface. This is the application-layer interface in my design. HBE does not use all of the pins, however. There are a handful that are not driven hard and have a weak pull-up. These will be used in the second mode, MPSSE. This mode allows for bit-banging on those same pins that HBE does not use and these pins are connected to the 10-pin USB Blaster connector that joins the EEPROM and FPGA.

The plan is to disable the FPGA by setting nCE pin high and then bit-bang the interface to the EEPROM. Once this is done, the FPGA can power up and load itself.

A generalized bit-banging code example and a command processing implementation for the EEPROM is what I was hoping to find online. Written in Python, of course. :slight_smile:

If you use the FTDI supplied drivers you can write the configuration device as you describe by pulling nConfig low putting all IO pins in weak pull-up, I don’t know about setting nCE high but that should then disable the DCLK etc? Encapsulating FTDI D2XX device driver with ctypes should make things easy.

Later switching to HBE mode requires that the FTDI pin driving DCLK is also connected to another FPGA IO-pin.

Some python code: may help you on your way?

Using the FT2232H part in MPSSE mode, and by porting the Intel/Altera SRunner source code to Python, I was able to program my ECPQ4A serial memory that boots the Cyclone 10. It works fine, albiet slower than I would like.

Thank you all for your consideration of my problem.

That’s good news :slight_smile:

Yep, MPSSE mode is very slow.