Saving testbench data to file (solved)

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  1. In the below link, I tried to saved the simulation-data in the file. Do you have any suggestion for this, or is it fine? This looks fine to me, but need advice as I am new to MyHDL (only 10 days experience).

    http://fpga-designs-with-myhdl.readthedocs.io/en/latest/myhdl/testbench.html#saving-data-to-file

  2. I am trying to convert my VHDL/Verilog templates into MyHDL-templates. Currently, I am following MyHDL official doc only. Do you have some more suggestions for other resources?

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This might be of some help : MyHDL cheat sheet
I started a tips and tricks but it is far from publishable.

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Just had a very quick look at your code.
Instead of modifying clk to an int, you can print with (“0”, “1”)[clk].
Another possibility is to create a Bool class inheriting bool and overcharging str method.

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