Variables in VHDL

I want to convert a piece of VHDL to MyHDL. In this piece of VHDL which is a clocked process they use variables instead of signals (not my choice). It looks like this:

 ***if rising_edge (Clk) then***

*** if (ResetError = ‘1’) then***
*** v_OutputFormat := c_IDLE;***
*** v_OutputData := (others => ‘0’);***

v_OutputFormat and v_OutputData are defined in the process as variables.

Can I write MyHDL is such a way that I get in the converted VHDL also variables? Using “.next” would create “Signals” and that will change the timing of the design.

Thanks in advance.

This will set you on your way
Read also the other replies …


thanks for the information about my question. Will have a look into it.

Albert Hoevenaars

I don’t think this statement holds. If you use those signals in a (separate) combinatorial process and register the final in the (original) clocked process, timing and routing will achieve the same results.