MyHDL

Verilog generate for always blocks in myhdl

Hi,

is it possible to write code in myhdl which serves the same purpose as “generate” keyword in Verilog for always blocks.
Does the converted code then represents the correct hardware behavior.
I did not find any example in my search.

Thanks!
Aurang

All the Python code outside of a myhdl generator is elaboration code, similar to V* generate statements. But the Python/myhdl is more powerful, you have all the features of Python in the elaboration phase (code outside of myhdl.instance, myhdl.always, myhdl.always_seq, and myhdl.always_comb).

Regards,
Chris

Here is an example in the manual: http://docs.myhdl.org/en/stable/manual/structure.html#inferring-the-list-of-instances

Thanks for your quick clarification.

Regards,
Aurang

Let us know if you have more questions or need more examples.