Xilinx library for MyHDL


I have created a XILINX primitive components library to be used with MyHDL.
Here it is :


Thanks for sharing! This is a comment request / need from users this will be useful. I will check it out when I have some free time.

@cfelton : This is still work in progress. I have not tried a full design with it. Also, simple examples have been written only for the demo. So, they have not been tested.

Of course, comments are welcome.

@DrPI It looks like a really interesting approach. It would be really interesting to see if this can feed into the Ovenbird project for integrating with Vivado.

@hgomersall Xilinx Unisim Library is the opposite of Ovenbird. It manages “raw” elements like bufg, dll, GTX…
As you know, “raw” does not mean simple and some elements are so complex (gtx, pcie…) that they can’t be managed directly. Then comes Xilinx IPs and Ovenbird.
I’ll have to read again the example and source code to fully understand how it works.

@DrPi I don’t quite know what you mean by opposite, but I agree they are not the same. Ovenbird is concerned with representing Vivado “aware” concepts through MyHDL. At the minute this is simulation and IP (crucially, encrypted IP). A separate task is to actually create those representations :slight_smile:.

Well, I mean, Xilinx Unisim library describes silicon primary elements while Ovenbird is used to describe high level IPs.

Will these representations be added to Ovenbird or will you create a separate repository for them ?

I am especially interested in FIFOs since this is the IP I use the most.

No plans at the moment, but keen to begin one if it’s useful. I’m sure you’ve noted, only the DSP48E1 exists at the moment…

Sure. That disappointed me :grin:

Actually, that’s not quite correct - I have a bit of a block ram implementation.