I am currently working on a myhdl project (link here), and am facing a problem while converting a myhdl module to VHDL. I am a beginner in myhdl, and I don’t know what i am doing wrong: I receive a
List of signals as a port is not supported: mem ConvertionError on the
Shouldn’t a memory module be represented as a list of signal? If not, how should I do it for it to be instantiable?
As a side question: Do I have to store the memory inside the block MemController (I actually want to have multiple reading heads in the future, for the same memory…)? If so, how should I do it?
Any help will be appreciated!