I’ve been integrating a so far experimental yosys backend into MyHDL that directly creates synthesizeable module hierarchies without the transfer through V* languages.
It’s now at a stage where you can get simple designs spinning and verified (using post-map Co-Simulation of generated Verilog).
To make this easy to play with, it’s packed into a Jupyter notebook powered virtual machine that you can run as a binder or locally. It’s found here:
(the Binder button will start the VM on mybinder)
In short, you can, out of the browser:
- Co-Simulate MyHDL units against synthesized Verilog
- Display waveforms and RTL elements
- Synthesize for a ECP5 target (for now)
- Program your FPGA board (when running as a local container on linux)
- Run automated tests
Progress updates and some details on the project are here:
Examples/howtos/exercises are checked out inside the Binder from a secondary playground.
Any enhancements, bug reports or more use cases are of course welcome (i.e. feel free to submit your notebooks that [don’t] work)