As a follow up: This project is going to be buried in favor of a next generation ‘kernel’ approach.
While serving some educational purpose, it turned out to cause more maintenance work and exposed a lot more limitations than expected, apart from the political issues (A future for the MyHDL community? - #77 by josyb)
So all new development will be going into the IRL based (intermediate representation language) kernel that is digesting myHDL syntax (up to some point). Entry page (Jupyter Notebooks as the above) and more info:
This is still regarded as possible future music and not intended for MyHDL beginners.
Although a few larger legacy projects were ported and verified to simulate/synthesize through the yosys back ends, it may still be necessary to rely on a proper verification of the emitted VHDL models, so: primarely for educational use.
Unlike the above jupyosys branch, I’ve taken a different approach to play with the relatively new CXXRTL simulation yosys backend that generates loadable DLL from RTL primitives. That one is again driven from a myHDL style test bench as usual, so several mapping stages can be co-verified in a more efficient way than going through verilog-based co-simulation - provided that CXXRTL path can be trusted (which seems so for synchronous designs).