Initial values, memories, and Yosys

The pairs of underscores got lost in copying, have just checked to make sure.

The verilog memory code could be the same, but the model also builds the RAM initialization block with a memory content values list. I have not found another way to attach this section to the generated verilog code.

See: http://murray-microft.co.uk/MyHDL/myram_2020-03-31_1745_SimRunsJust_SynthGood.tar.gz