Instantiating FPGA components
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7
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2080
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February 2, 2019
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Could modbv support non powers of two?
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10
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1195
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December 23, 2018
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Coalesce identical sequential blocks into the same block?
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9
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1019
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December 22, 2018
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Conversion hierarchy extraction?
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8
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852
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December 10, 2018
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Combinational tree like accumulatioin
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6
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1048
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December 10, 2018
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Cosimulation myhdl.vpi search path
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2
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3393
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November 8, 2018
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VHDL Bit string representation
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15
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2051
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November 5, 2018
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Using standart Python modules
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2
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755
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October 10, 2018
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ORConf 2018: need someone to represent myhdl
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5
|
972
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October 7, 2018
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Verilog width expansion and reduction operator equivalence?
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2
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1655
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October 6, 2018
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Invoke Verilog generate for Python list handling
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1
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1254
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October 1, 2018
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How to use counters similiar to verilog using for loops?
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10
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979
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September 25, 2018
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Variables in VHDL conversion
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15
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1363
|
September 5, 2018
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I don't get how to convert to VHDL
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3
|
840
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September 3, 2018
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Formal methods and MyHDL
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|
2
|
997
|
August 29, 2018
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From myHDL to syntesis
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8
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1031
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August 7, 2018
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Is it sensible to yield a delay of zero?
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3
|
788
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August 1, 2018
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VHDL conversion - missing constant
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3
|
1167
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July 31, 2018
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Convert FROM vhdl
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1
|
772
|
July 20, 2018
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Requirement: 800+ function inputs/outputs (pinmux)
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17
|
1253
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July 10, 2018
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Add new Bool type to MyHDL?
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9
|
917
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July 5, 2018
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Verify the discussions can be discussed
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5
|
813
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July 3, 2018
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Matching a signal against a bitvector
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9
|
1399
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July 1, 2018
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Explicitly listing instances and instances() give different output (solved)
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2
|
782
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June 4, 2018
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Conversion of list of objects
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1
|
738
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June 1, 2018
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Instances are renamed every time in MyHDL 0.10
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3
|
1137
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May 4, 2018
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Instance-specific constants in VHDL conversion
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16
|
2359
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April 16, 2018
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Myhdl 0.10 release
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13
|
1508
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April 14, 2018
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Porting out a list of 8 bools as an 8-bit vector
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6
|
821
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April 13, 2018
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Grabbing a bit from a configuration register
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2
|
687
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April 10, 2018
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