|
Grabbing a bit from a configuration register
|
|
2
|
770
|
April 10, 2018
|
|
myhdl.AlwaysCombError: signal used as inout in always_comb function argument
|
|
3
|
1553
|
April 10, 2018
|
|
Inverting a signal passed into a module
|
|
2
|
809
|
April 5, 2018
|
|
Biquad filter produces garbage (solved)
|
|
6
|
1023
|
April 5, 2018
|
|
Connecting signals between modules
|
|
2
|
890
|
April 4, 2018
|
|
Exception raised on reset signal
|
|
6
|
1042
|
April 4, 2018
|
|
Moving to 0.1dev broke my design
|
|
1
|
1028
|
March 23, 2018
|
|
Iterating over a group of elements
|
|
3
|
1059
|
March 22, 2018
|
|
Multi-bit latch
|
|
4
|
902
|
March 22, 2018
|
|
Py.test fails on Ubuntu 16.04
|
|
2
|
1571
|
February 10, 2018
|
|
Verilog generate for always blocks in myhdl
|
|
4
|
1186
|
January 22, 2018
|
|
Conversion producing invalid register names
|
|
9
|
1416
|
January 5, 2018
|
|
[FAQ] Contributing to MyHDL
|
|
0
|
1139
|
November 10, 2017
|
|
Issues and PRs are piling up
|
|
4
|
1770
|
November 6, 2017
|
|
Signals in objects vs. function arguments or method calls
|
|
8
|
1315
|
November 1, 2017
|
|
Testbench conversion (solved)
|
|
11
|
2098
|
October 16, 2017
|
|
VHDL-open equivalent in MyHDL (solved)
|
|
16
|
1979
|
October 16, 2017
|
|
Saving testbench data to file (solved)
|
|
2
|
1220
|
October 16, 2017
|
|
How to pass part of the signal to module
|
|
2
|
1088
|
October 13, 2017
|
|
REG intialization without 'always_seq' (solved)
|
|
4
|
1021
|
October 11, 2017
|
|
'concat' not working (solved)
|
|
4
|
1347
|
October 10, 2017
|
|
Help: SDR, DSP, FPGAs and Gnuradio
|
|
4
|
1430
|
October 9, 2017
|
|
VHDL conversion bug (resize of signed signal)?
|
|
4
|
3275
|
October 5, 2017
|
|
Sort signal declarations in generated VHDL
|
|
3
|
1084
|
October 5, 2017
|
|
VHDL block equivalent in MyHDL?
|
|
12
|
1511
|
September 25, 2017
|
|
Python comments into generated verilog as comments
|
|
9
|
1379
|
September 11, 2017
|
|
Synthesisable TristateSignal
|
|
17
|
4682
|
September 8, 2017
|
|
GSoC #6: Round Modes and Their Behavior
|
|
4
|
1443
|
August 30, 2017
|
|
GSoC #-1: Work Product Summary
|
|
0
|
1316
|
August 26, 2017
|
|
GSoC #8: MyHDL Back-end Source Code Analysis (1)
|
|
0
|
1233
|
August 13, 2017
|