Moving to 0.1dev broke my design
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1
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963
|
March 23, 2018
|
Iterating over a group of elements
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3
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970
|
March 22, 2018
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Multi-bit latch
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4
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787
|
March 22, 2018
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Py.test fails on Ubuntu 16.04
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2
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1459
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February 10, 2018
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Verilog generate for always blocks in myhdl
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4
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1079
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January 22, 2018
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Conversion producing invalid register names
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9
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1265
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January 5, 2018
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[FAQ] Contributing to MyHDL
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0
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1076
|
November 10, 2017
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Issues and PRs are piling up
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4
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1597
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November 6, 2017
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Signals in objects vs. function arguments or method calls
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8
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1132
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November 1, 2017
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Testbench conversion (solved)
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11
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1883
|
October 16, 2017
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VHDL-open equivalent in MyHDL (solved)
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16
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1710
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October 16, 2017
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Saving testbench data to file (solved)
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2
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1127
|
October 16, 2017
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How to pass part of the signal to module
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2
|
1008
|
October 13, 2017
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REG intialization without 'always_seq' (solved)
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4
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904
|
October 11, 2017
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'concat' not working (solved)
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4
|
1230
|
October 10, 2017
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Help: SDR, DSP, FPGAs and Gnuradio
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4
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1257
|
October 9, 2017
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VHDL conversion bug (resize of signed signal)?
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4
|
2973
|
October 5, 2017
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Sort signal declarations in generated VHDL
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3
|
990
|
October 5, 2017
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VHDL block equivalent in MyHDL?
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|
12
|
1358
|
September 25, 2017
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Python comments into generated verilog as comments
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|
9
|
1238
|
September 11, 2017
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Synthesisable TristateSignal
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17
|
4245
|
September 8, 2017
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GSoC #6: Round Modes and Their Behavior
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4
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1345
|
August 30, 2017
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GSoC #-1: Work Product Summary
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0
|
1235
|
August 26, 2017
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GSoC #8: MyHDL Back-end Source Code Analysis (1)
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0
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1127
|
August 13, 2017
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Using decorators for common hardware structures
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|
0
|
1073
|
August 8, 2017
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Weird register behavior during simulation
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2
|
1064
|
August 6, 2017
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GSoC #7: Overflow Modes
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0
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960
|
August 1, 2017
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Variable semantics
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|
7
|
1156
|
August 1, 2017
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Conversion from VHDL problems
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|
4
|
1334
|
July 25, 2017
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GSoC #5: Sum Problem of Fixed-Point Type
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|
0
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983
|
July 25, 2017
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